Many applications rely on captured or recorded waveform data for a variety of purposes, such as signal measurement or characterization. Often, one or more signal waveforms, such as stimulus and response waveforms, are recorded and then analyzed to determine one or more parameters of interest. Such processing may be involved, such as in performing spectral analysis of captured data, or may be relatively straightforward, as in identifying signal transitions within a signal waveform.
One characteristic common to most data recording applications is the accumulation of potentially large data sets. For example, consider that sampling a signal at ten megahertz for a hundred microseconds generates a thousand sample points. Where high-speed sampling is involved or where multiple waveforms are simultaneously sampled, the number of accumulated data samples builds quickly. For example, in the above-incorporated patent application, a tapped delay line high-speed register (the xe2x80x9cTDLRxe2x80x9d) captures one or more channels of high-speed data based on digitizing laser-based distance measuring waveforms.
Often, data is collected or captured in one location or sub-system, and then processed in another. The challenge then is to make these large accumulated data sets available for processing in timely fashion, which may be problematic in terms of moving the data around within a processing system where data transport speeds are practically limited.
Indeed, in some instances, moving large amounts of capture data around within a processing system may prove impractical, or at least undesirable. Thus, an approach to handling waveform data in a way that minimizes the need for transporting it between processing subsystems would reduce overhead. This reduction in overhead may be particularly advantageous in processing systems with limited bandwidth, or with extensive, real-time processing activities that limit the systems"" ability to devote much processing time to data transport between processing sub-systems.
The present invention is an apparatus and method for data reduction, particularly in the context of processing digitized waveform data. In applications where potentially large series of digitized waveform data must be managed, the present invention provides data clustering techniques that provide salient waveform information, such as information about waveform transitions, while reducing or eliminating the need for an associated processing system to retrieve the full set of waveform data.
As applied to the TDLR for waveform digitization as disclosed in application Ser. No. 09/728,567, the present invention processes one or more digitized waveforms (capture channel data) and provides a supporting or associated processor with a reduced data set comprising salient waveform information. In particular, clustering in this application provides the supporting processor with sample numbers corresponding to signal transitions, thus eliminating the need for the system processor to examine potentially lengthy sequences of waveform samples to detect such transitions.
As an example, a waveform may be digitized as a sample set of discrete waveform samples, recorded as ones or zeros depending on whether the sampled waveform was above or below a reference threshold at each sample instant. Capture post-processing in accordance with one embodiment of the present invention entails processing the sequence of binary values to identify which samples correspond to signal transitions. As an illustration, assume the capture data consists of five hundred sequential samples, with a zero-to-one transition at the one-hundredth sample and a subsequent one-to-zero sample at the three-hundredth sample. Post-processing reduces the sample set to identification of these signal transition points, greatly reducing the information that must be transferred to the system processor.
Post-processing may be implemented as a data reduction circuit using a microcontroller or microprocessor, but is preferably implemented using programmable logic or using custom integrated circuits. Implementation of the post-processing functionality in logic circuitry permits substantially parallel processing of the captured waveform data, allowing fast data reduction operation. The post-processor circuit may also serve other functions in accordance with particular system needs. For example, with respect to the TDLR, the post-processor circuit may provide a data and test interface between the TDLR and the main system processor.